CAES announced on Monday that the company secured a contract from Vinnova, a Swedish government agency committed to promoting innovation, developing next-generation RISC-V-based space computing capabilities.
The RISC-V developments will enable future CAES microprocessors to control spacecraft, create high-performance payload processing and feature timing isolation for software applications and prevent interference from other system components.
“We look forward to working with Vinnova and our project partners to enhance our RISC-V processor technology to meet our customers’ next-generation space program needs,” commented Mike Kahn, CAES’ president and CEO as well as a 2021 Wash100 Award recipient.
“Our space systems team is fully prepared to address the market’s growing need for cybersecurity and create the next generation of trusted, radiation-hardened processors with both RISC-V and SPARC/LEON architectures to enable low risk, high-performance implementation for space applications,” added Kahn.
The NOEL-V fault-tolerant, 64-bit processor core is based on the open RISC-V instruction set architecture. It builds upon CAES’ heritage with the SPARC/LEON architecture. It also marks the newest addition to CAES’ trusted fault-tolerant space computing product portfolio.
“The results of this initiative with Vinnova will inform our future radiation-hardened NOEL-V microprocessor development in collaboration with the European Space Agency. Our team plans to publish the results and disseminate the technology to benefit the industry at large,” stated Sandi Habinc, CAES general manager of Gaisler Products.
As soon as a multi-core NOEL-V processor development platform will be tested through a partnership with Chalmers University of Technology and atsec, an independent laboratory focused on information security. The tests will ensure strong security towards higher software layers.
“Chalmers’ collaboration on the LEON processor development dates back to 1997. We are excited to continue this long-standing collaboration on the RISC-V processor architecture as part of the Vinnova activity,” added Stefan Bengtsson, president and CEO of Chalmers University of Technology.